Semiconductor electroplating system

ABSTRACT

A semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The conducting ring has at least two connecting points. The wafer has a first surface and an opposite second surface. An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.

RELATED APPLICATIONS

This application claims priority to U.S. Provisional Application Ser.No. 62/153,400 filed Apr. 27, 2015, and Taiwan Application Serial Number104126716, filed Aug. 17, 2015, the disclosures of which areincorporated herein by reference in their entireties.

BACKGROUND

1. Field of Invention

The present invention relates to a semiconductor electroplating system.

2. Description of Related Art

A typical RF sensor includes a chip package and passive components. Thepassive components can be, for example, inductors. And the chip packageis used as an active component. Both the chip package and the inductorsare disposed on a printed circuit board, and the inductors are placedoutside the chip package.

That is to say, after the chip package is manufactured, additional andindependent inductors are required to be arranged on the printed circuitboard to allow the RF sensor working properly. However, it leads to alot of assembly time for the RF sensor, and makes it difficult to reducethe cost of the inductors. Moreover, additional space and circuits needto be reserved on the printed circuit board, thereby causing designinconvenience.

SUMMARY

An aspect of the present invention is to provide a chip package.

According to an embodiment of the present invention, a chip packageincludes a chip, an isolation layer and a redistribution layer. The chiphas a substrate, an electrical pad and a protection layer. The substratehas a first surface and an opposite second surface. The protection layeris located on the first surface, and the electrical pad is located inthe protection layer. The substrate has a through hole, and theprotection layer has a concave hole, such that the electrical pad isexposed through the concave hole and the through hole. The isolationlayer is located on the second surface, a sidewall of the through hole,and a sidewall of the concave hole. The redistribution layer includes aconnection portion and a passive component portion. The connectionportion is located on the isolation layer and in electrical contact withthe electrical pad. The passive component portion is located on theisolation layer that is on the second surface, and an end of the passivecomponent portion is connected to the connection portion that is on thesecond surface.

Another aspect of the present invention is to provide a manufacturingmethod of a chip package.

According to an embodiment of the present invention, a manufacturingmethod of a chip package includes the following steps. The manufacturingmethod of a chip package includes the following steps. A temporaryadhesive layer is used to attach a carrier to a wafer. The wafer has asubstrate, an electrical pad and a protection layer. The substrate has afirst surface and an opposite second surface. The protection layer islocated on the first surface, and the electrical pad is located in theprotection layer. The second surface of the substrate is etched to forma through hole in the substrate. The protection layer in the throughhole is etched, such that a concave hole is formed in the protectionlayer, and the electrical pad is exposed through the concave hole andthe through hole. An isolation layer is formed on the second surface, asidewall of the through hole, and a sidewall of the concave hole. Aredistribution layer is formed on the isolation layer and the electricalpad. The redistribution layer is patterned to simultaneously form aconnection portion and a passive component portion in the redistributionlayer. The connection portion is located on the isolation layer and inelectrical contact with the electrical pad. The passive componentportion is located on the isolation layer that is on the second surface,and an end of the passive component portion is connected to theconnection portion that is on the second surface.

In the aforementioned embodiments of the present invention, since theredistribution layer of the chip package has a passive componentportion, the chip package thereby has both the functions of an activecomponent and of an passive component. For example, the passivecomponent portion can be used as the inductor of the chip package. Whilepatterning the redistribution layer, both the passive component portionand the connection portion are formed simultaneously, such that thepassive component portion is formed on the isolation layer that is onthe second surface of the substrate. Hence, the required time formanufacturing the passive component portion may be saved. The chippackage of the present invention may be used as a RF sensor which do notrequire a typical independent inductor but still has an inductorfunction. As a result, both the assembly time of the chip package andthe cost can be saved, since no typical inductor is required. Besides, aprinted circuit board for placing the chip package does not need toreserve space and wires for disposing the typical inductor, therebyenhancing the design convenience.

Another aspect of the invention is to provide a semiconductorelectroplating system.

According to an embodiment of the present invention, a semiconductorelectroplating system includes a conducting ring and at least oneconductive device. The conducting ring is used for carrying a wafer. Theconducting ring has at least two connecting points. The wafer has afirst surface and an opposite second surface. An isolation layer islocated on the second surface. Two ends of the conductive device arerespectively connected to the two connecting points of the conductingring. When the conducting ring is immersed in the plating solution andis energized, a redistribution layer that is to be patterned is formedon the isolation layer. The conductive device is used for transmitting apartial current that passes through one of the connecting points to theother connecting point.

Another aspect of the invention is to provide a semiconductorelectroplating system.

According to an embodiment of the present invention, a semiconductorelectroplating system includes a conducting ring and at least oneconductive piece. The conducting ring is used for carrying a wafer. Theconducting ring has a ring-shaped track. The wafer has a first surfaceand an opposite second surface. The isolation layer is located on thesecond surface. Each of two ends of the conductive piece has aconnecting point. Each of the connecting points is movably connected tothe ring-shaped track of the conducting ring, and the conductive pieceoverlaps a portion of the conducting ring. When the conducting ring isimmersed in the plating solution and is energized, a redistributionlayer that is to be patterned is formed on the isolation layer. Theconductive piece is used for transmitting a partial current that passesthrough one of the connecting points to the other connecting point.

It is to be understood that both the foregoing general description andthe following detailed description are by examples, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the followingdetailed description of the embodiment, with reference made to theaccompanying drawings as follows:

FIG. 1 is a cross-sectional view of a chip package according to anembodiment of the present invention;

FIG. 2 is a schematic view of a layout of a redistribution layer of thechip package shown in FIG. 1;

FIG. 3 is a flow chart of a manufacturing method of a chip packageaccording to an embodiment of the present invention;

FIG. 4 is a cross-sectional view of a wafer after being attached by acarrier according to an embodiment of the present invention;

FIG. 5 is a cross-sectional view of a substrate shown in FIG. 4 afterbeing ground;

FIG. 6 is a cross-sectional view of a through hole after being formed inthe substrate shown in FIG. 5;

FIG. 7 is a cross-sectional view of a concave hole after being formed ina protection layer shown in FIG. 6;

FIG. 8 is a cross-sectional view of an isolation layer after beingformed on a second surface, a sidewall of the through hole, and asidewall of the concave hole shown in FIG. 7;

FIG. 9 is a cross-sectional view of the redistribution layer after beingformed on the isolation layer and the electrical pad shown in FIG. 8;

FIG. 10 is a cross-sectional view of a conductive structure after beingformed on the redistribution layer shown in FIG. 9;

FIG. 11A is a cross-sectional view of a chip package according toanother embodiment of the present invention;

FIG. 11B is a schematic view of a layout of a redistribution layer ofthe chip package shown in FIG. 11A;

FIG. 12A is a cross-sectional view of a chip package according tofurther another embodiment of the present invention;

FIG. 12B is a schematic view of a layout of a redistribution layer ofthe chip package in FIG. 12A;

FIG. 12C is another embodiment of FIG. 12B;

FIG. 13 is a cross-sectional view of a chip package according to furtheranother embodiment of the present invention;

FIG. 14 is a cross-sectional view of a chip package according to furtheranother embodiment of the present invention;

FIG. 15 is a flow chart of an operating method of a semiconductorelectroplating system according to an embodiment of the presentinvention;

FIG. 16 is a top view of a semiconductor electroplating system accordingto an embodiment of the present invention;

FIG. 17 is a cross-sectional view of the semiconductor electroplatingsystem taken along line 17-17 shown in FIG. 16;

FIG. 18 is a cross-sectional view of a redistribution layer that is tobe patterned after being formed on an isolation layer shown in FIG. 8through the semiconductor electroplating system shown in FIG. 16;

FIG. 19 is a top view of a semiconductor electroplating system accordingto an embodiment of the present invention;

FIG. 20 is a flow chart of an operating method of a semiconductorelectroplating system according to an embodiment of the presentinvention; and

FIG. 21 is a top view of a semiconductor electroplating system accordingto an embodiment of the present invention.

DETAILED DESCRIPTION

Reference will now be made in detail to the present embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

FIG. 1 is a cross-sectional view of a chip package 100 according to anembodiment of the present invention. FIG. 2 is a schematic view of alayout of a redistribution layer 130 of the chip package 100 shown inFIG. 1. As shown in FIG. 1 and FIG. 2, the chip package 100 includes achip 110, an isolation layer 120, and a redistribution layer (RDL) 130.The chip 110 has a substrate 112, an electrical pad 114 and a protectionlayer 116. The substrate 112 has a first surface 111 and an oppositesecond surface 113. The protection layer 116 is located on the firstsurface 111. The electrical pad 114 is located in the protection layer116. The substrate 112 has a through hole 115, and the protection layer116 has a concave hole 117, such that the electrical pad 114 is exposedthrough the concave hole 117 and the through hole 115. The isolationlayer 120 is located on the second surface 113, the sidewall of thethrough hole 115, and the sidewall of the concave hole 117. Theredistribution layer 130 includes a connection portion 132 and a passivecomponent portion 134. The connection portion 132 is located on theisolation layer 120 and in electrical contact with the electrical pad114. The passive component portion 134 is located on the isolation layer120 that is on the second surface 113, and an end of the passivecomponent portion 134 is connected to the connection portion 132 that ison the second surface 113.

In this embodiment, the chip package 100 may be a RF sensor, but thepresent invention is not limited in this regard. The substrate 112 maybe made of a material including silicon. The protection layer 116 mayinclude inter-layer dielectric (ILD), inter-metal dielectric (IMD), andpassivation layer. The redistribution layer 130 may be made of amaterial including aluminum or copper, and the physical vapor deposition(PVD) method or the electroplating method may be used to form theredistribution layer 130 that covers the isolation layer 120 and theelectrical pad 114, then a patterning process is used to simultaneouslyform the connection portion 132 and the passive component portion 134 inthe redistribution layer 130. The patterning process may includephotolithography techniques, such as exposure, developing and etching.

Since the redistribution layer 130 of the chip package 100 has a passivecomponent portion 134, the chip package 100 thereby has both thefunction of a active component and a passive component. For instance,the passive component portion 134 can be used as the inductor of thechip package 100. The chip package 100 of the present invention has theinductor function without needing a conventional independent inductor.As a result, both the assembly time of the chip package and the cost canbe saved, since no typical inductor is needed.

While patterning the redistribution layer 130, the passive componentportion 134 and the connection portion 132 are formed simultaneously,such that the passive component portion 134 is formed on the isolationlayer 120 that is on the second surface 113 of the substrate 112. Hence,the required time for manufacturing the passive component portion 134 issaved. In addition, a printed circuit board for placing the chip package100 does not need to reserve space and wires for disposing a typicalinductor, thereby enhancing the design convenience.

In this embodiment, the shape of the passive component portion 134 isU-shaped, however, it is not a restriction of the present invention.Designers can design the layout scheme of the redistribution layer 130according to the design requirement, to change the shape of the passivecomponent portion 134.

The chip package 100 further includes a barrier layer 140 and aconductive structure 150. The barrier layer 140 is located on theredistribution layer 130 and the isolation layer 120 that is on thesecond surface 113. The barrier layer 140 has an opening 142 to exposethe connection portion 132. The conductive structure 150 is located onthe connection portion 132 that is in the opening 142 of the barrierlayer 140, such that the conductive structure 150 is electricallyconnected to the electrical pad 114 through the connection portion 132of the redistribution layer 130. The conductive structure 150 may be asolder ball or a conductive bump of a ball grid array (BGA). Moreover,the chip package 100 may selectively has a cavity 160. The cavity 160 islocated between the barrier layer 140 and the connection portion 132that is in the through hole 115.

The manufacturing method of the chip package 100 will be described inthe following descriptions.

FIG. 3 is a flow chart of a manufacturing method of a chip packageaccording to an embodiment of the present invention. The manufacturingmethod of the chip package includes the following steps. In step S1, atemporary adhesive layer is used to attach a carrier to a wafer. Thewafer has a substrate, an electrical pad and a protection layer. Thesubstrate has a first surface and an opposite second surface. Theprotection layer is located on the first surface, and the electrical padis located in the protection layer. Next, in step S2, the second surfaceof the substrate is etched to form a through hole in the substrate.Thereafter, in step S3, the protection layer in the through hole isetched, such that a concave hole is formed in the protection layer, andthe electrical pad is exposed through the concave hole and the throughhole. Next, in step S4, an isolation layer is formed on the secondsurface, a sidewall of the through hole, and a sidewall of the concavehole. Thereafter, in step S5, a redistribution layer is formed on theisolation layer and the electrical pad. Finally, in step S6, theredistribution layer is patterned to simultaneously form a connectionportion and a passive component portion in the redistribution layer. Theconnection portion is located on the isolation layer and in electricalcontact with the electrical pad. The passive component portion islocated on the isolation layer that is on the second surface, and an endof the passive component portion is connected to the connection portionthat is on the second surface. The details of the aforementioned stepswill be described in the following descriptions.

FIG. 4 is a cross-sectional view of a wafer 110 a after being attachedby a carrier 204 according to an embodiment of the present invention.FIG. 5 is a cross-sectional view of the substrate 112 shown in FIG. 4after being ground. In the following description, wafer 110 a isreferred to as a semiconductor structure that includes plural chips 110of FIG. 1 before a cutting process. The wafer 110 a has the substrate112, the electrical pad 114, and the protection layer 116. As shown inFIG. 4 and FIG. 5., a temporary adhesive layer 202 is used to attach acarrier 204 onto a wafer 110 a. The carrier 204 may be made of amaterial including a glass, for providing the support strength of thewafer 110 a. Next, the second surface 113 of the substrate 112 may beground, such that the thickness of the substrate 112 is reduced from D1to D2.

FIG. 6 is a cross-sectional view of the through hole 115 after beingformed in the substrate 112 shown in FIG. 5. FIG. 7 is a cross-sectionalview of the concave hole 117 after being formed in the protection layer116 shown in FIG. 6. As shown in FIG. 6 and FIG. 7, after the thicknessof the substrate 112 is reduced, the second surface 113 of the substrate112 may be etched, such that the through hole 115 which aligned with theelectrical pad 114 is formed in the substrate 112. Next, the protectionlayer 116 in the through hole 115 is etched, such that a concave hole117 aligned with the electrical pad 114 is formed in the protectionlayer 116. As a result, the electrical pad 114 is exposed through theconcave hole 117 and the through hole 115.

FIG. 8 is a cross-sectional view of the isolation layer 120 after beingformed on the second surface 113, the sidewall of the through hole 115,and the sidewall of the concave hole 117 shown in FIG. 7. FIG. 9 is across-sectional view of the redistribution layer 130 after being formedon the isolation layer 120 and the electrical pad 114 shown in FIG. 8 Asshown in FIG. 8 and FIG. 9, after the electrical pad 114 is exposedthrough the concave hole 117 and the through hole 115, the isolationlayer 120 may be formed on the second surface 113 of the substrate 112,the sidewall of the second surface 113, the sidewall of the through hole115, and on the sidewall of the concave hole 117. The isolation layer120 may be formed by a patterning process, such that at least oneportion of the electrical pad 114 is covered by the isolation layer 120.

After the isolation layer 120 is formed, the redistribution layer 130may be formed on the isolation layer 120 and the electrical pad 114.Next, the redistribution layer 130 is patterned to form the connectionportion 132 and the passive component portion 134 simultaneously. Theconnection portion 132 is located on the isolation layer 120 and inelectrical contact with the electrical pad 114. The passive componentportion 134 is located on the isolation layer 120 that is on the secondsurface 113, and an end of the passive component portion 134 isconnected to the connection portion 132 that is on the second surface113.

FIG. 10 is a cross-sectional view of the conductive structure 150 afterbeing formed on the redistribution layer 130 shown in FIG. 9. As shownin FIG. 9 and FIG. 10, after the redistribution layer 130 is patternedto form the connection portion 132 and the passive component portion134, the barrier layer 140 may be formed on the redistribution layer 130and the isolation layer 120 that is on the second surface 113. Next, thebarrier layer 140 is patterned to form an opening 142, such that theconnection portion 132 of the redistribution layer 130 is exposedthrough the opening 142. Then, the conductive structure 150 may beformed on the connection portion 132 that is in the opening 142 of thebarrier layer 140, such that the conductive structure 150 iselectrically connected to the electrical pad 114 through the connectionportion 132.

After the conductive structure 150 is formed, the carrier 204, the wafer110 a, the isolation layer 120 and the barrier layer 140 may be cutalong line L-L. Next, the temporary adhesive layer 202 may be irradiatedwith ultraviolet light, raise the temperature, or be immersed in achemical liquid, such that the adhesion of the temporary adhesive layer202 is removed. As a result, the carrier 204 can be removed and therebyforming the chip package 100 of FIG. 1.

It is to be noted that the connection relationships and materials of theelements described above will not be repeated in the followingdescription, and only aspects related to other types of chip packagewill be described.

FIG. 11A is a cross-sectional view of a chip package 100 a according toanother embodiment of the present invention. FIG. 11B is a schematicview of the layout of the redistribution layer 130 of the chip package100 a shown in FIG. 11A. As shown in FIG. 11A and FIG. 11B. The chippackage 100 a includes the chip 110, the isolation layer 120 and theredistribution layer 130. The redistribution layer 130 includes theconnection portion 132 and the passive component portion 134. Thedifference between this embodiment and the embodiment shown in FIG. 1and FIG. 2 is that herein the passive component portion 134 is planarspiral-shaped. The chip 110 has a conducting wire L1 located on theprotection layer 116, and the conducting wire L1 is connected to theelectrical pad 114 and another adjacent electrical pad 114.

FIG. 12A is a cross-sectional view of a chip package 100 b according tofurther another embodiment of the present invention. FIG. 12B is aschematic view of the layout of the redistribution layer 130 of the chippackage 100 b in FIG. 12A. As shown in FIG. 12A and FIG. 12B, the chippackage 100 b includes the chip 110, the isolation layer 120, and theredistribution layer 130. The redistribution layer 130 includes theconnection portion 132 and the passive component portion 134. Thedifference between this embodiment and the embodiment shown in FIG. 1and FIG. 2 is that herein the passive component portion 134 isthree-dimensional spiral-shaped. That is to say, the passive componentportion 134 is not at the same level.

FIG. 12C is another embodiment of FIG. 12B. As shown in FIG. 12A andFIG. 12C, the chip package 100 b includes the chip 110, the isolationlayer 120, and the redistribution layer 130. The redistribution layer130 includes the connection portion 132 and the passive componentportion 134. The difference between this embodiment and the embodimentshown in FIG. 12B is that herein the chip 110 further includes amagnetic component 170, and the magnetic component 170 is surrounded bythe passive component portion 134 of the redistribution layer 130. Inthis exemplary embodiment, the magnetic component 170 can increase theinductance value of the chip package 100 b.

FIG. 13 is a cross-sectional view of a chip package 100 c according tofurther another embodiment of the present invention. The chip package100 c includes the chip 110, the isolation layer 120, and theredistribution layer 130. The redistribution layer 130 includes theconnection portion 132 and the passive component portion 134. The chip110 has the first electrical pad 114. The difference between thisembodiment and the embodiment shown in FIG. 1 is that herein the chip110 further includes a second electrical pad 114 a. The secondelectrical pad 114 a is located in the protection layer 116 and thefirst electrical pad 114 is located between the second electrical pad114 a and the substrate 112. Moreover, the protection layer 116 has anopening 118 to expose the second electrical pad 114 a. The conductivestructure 150 is located on the second electrical pad 114 a that is inthe opening 118 of the protection layer 116. The second electrical pad114 a may be electrically connected to the first electrical pad 114through a conductor that is in the protection layer 116.

FIG. 14 is a cross-sectional view of a chip package 100 d according tofurther another embodiment of the present invention. The chip package100 d includes the chip 110, the isolation layer 120, and theredistribution layer 130. The redistribution layer 130 includes theconnection portion 132 and the passive component portion 134. Thedifference between this embodiment and the embodiment shown in FIG. 13is that herein the chip package 100 d further includes a conductivelayer 180 and a barrier layer 140 a. The conductive layer 180 is locatedon a surface 119 of the protection layer 116 facing away from thesubstrate 112 and on the second electrical pad 114 a that is in theopening 118 of the protection layer 116. The barrier layer 140 a coversthe conductive layer 180 and the protection layer 116, and the barrierlayer 140 a has an opening 142 a to expose the conductive layer 180. Theconductive structure 150 is located on a conductive layer 180 that is inthe opening 142 a of the barrier layer 140 a, such that the conductivestructure 150 is electrically connect to the second electrical pad 114 athrough the conductive layer 180.

In the following description, a method for forming a redistributionlayer that is to be patterned with a uniform thickness after the processof FIG. 8 will be described.

FIG. 15 is a flow chart of an operating method of a semiconductorelectroplating system according to an embodiment of the presentinvention. After the isolation layer 120 of FIG. 8 is formed, in step S1a, two ends of at least one conductive device are respectively connectedto two connecting points of a conducting ring. Next, in step S2 a, thewafer having the isolation layer is disposed into the conducting ring.In step S3 a, the conducting ring is immersed in a plating solution.Finally, in step S4 a, the conducting ring is energized to from theredistribution layer that is to be patterned on the isolation layer. Apartial current passing through one of the connecting points transmitsto the other connecting point through the conductive device. The detailsof the aforementioned steps will be described in the followingdescriptions.

FIG. 16 is a top view of a semiconductor electroplating system 300according to an embodiment of the present invention. FIG. 17 is across-sectional view of the semiconductor electroplating system 300taken along line 17-17 shown in FIG. 16. As shown in FIG. 16 and FIG.17, the semiconductor electroplating system 300 includes a conductingring 310 and at least one conductive device 320. The conducting ring 310can be used to carry the semiconductor structure of FIG. 8. Theconducting ring 310 has at least two connecting points 318 a and 318 b.The connecting points 318 a and 318 b may be screws or blots, and theconductive device 320 may be an electric wire, but the present inventionis not limited in this regard. In operation, two ends 332 and 324 of theconductive device 320 may be respectively connected to the twoconnecting points 318 a and 318 b of the conducting ring 310, and theconductive device 320 is disposed along the edge of the conducting ring310. After the semiconductor electroplating system 300 in FIG. 16 isassembled, the wafer 110 a having the isolation layer 120 shown in FIG.8 may be disposed in the conducting ring 310.

In this embodiment, the conducting ring 310 has a top surface 312, asidewall 314, and a supporting surface 316 which are sequentiallyconnected. The connecting points 318 a and 318 b and the conductivedevice 320 are disposed on the top surface 312 of the conducting ring310. The sidewall 314 surrounds an accommodating space 311, and thesupporting surface 316 is protruded from the accommodating space 311,such that the top surface 312, the sidewall 314, and the supportingsurface 316 form a ladder structure. The accommodating space 311 canhold the wafer 110 a of FIG. 8, and the wafer 110 a can be disposed onthe supporting surface 316, such that the wafer 110 a is surrounded bythe sidewall 314. The first surface 111 of the wafer 110 a (frontsurface) faces the supporting surface 316.

After the wafer 110 a of FIG. 8 is disposed in the conducting ring 310,the conducting ring 310 and the wafer 110 a that has the electrical pad114 therein are immersed in a plating solution and are energized, suchthat the circuit can flow into the conducting ring 310 through theconducting wire 302. In this embodiment, the connecting point 318 a ofthe conducting ring 310 can be connected to the conducting wire 302 andto an end 332 of the conductive device 320 at the same time.

FIG. 18 is a cross-sectional view of the redistribution layer 130 thatis to be patterned after being formed on the isolation layer 120 shownin FIG. 8 through the semiconductor electroplating system 300 shown inFIG. 16. As shown in FIG. 16 and FIG. 18, after the conducting ring 310is energized, the redistribution layer 130 that is to be patterned canbe formed on the isolation layer 120. The conductive device 320 cantransmit a partial current that passes through the connecting point 318a to another connecting point 318 b, such that the redistribution layer130 on the second surface 113 (back surface) has a uniform thickness. Ifthere is no conductive device 320 disposed on the conducting ring 310,while energizing, due to the impedance of the conducting ring 310itself, and the distance which the current flows to the place adjacentto the connecting point 318 a of the conducting ring 310 is shorter thanthe distance which the current flows to the place adjacent to theconnecting point 318 b of the conducting ring 310, it is easy to causethe redistribution layer 130 adjacent to the connecting point 318 a isthicker than the redistribution layer 130 adjacent to the connectingpoint 318 b.

In this embodiment, the conductive device 320 on the conducting ring 310has the function of dispersing the current. When the wafer 110 a of FIG.8 located in the conducting ring 310 is immersed in the platingsolution, the conductive device 320 can lead a partial current thatpasses through the connecting point 318 a of the conducting ring 310 toa specific place (e.g., the connecting point 318 b), such that thethickness of the redistribution layer 130 formed adjacent to theconnecting point 318 a is reduced, and the thickness of theredistribution layer 130 formed adjacent to the connecting point 318 bis increased. Hence, the thickness uniformity of the redistributionlayer 130 that is to be patterned can be improved. As a result, thestandard deviation of each place of the redistribution layer 130 on thesecond surface 113 (back surface) of the wafer 110 a can be reduced to0.2 μm to 0.4 μm. The designer can change the positions of theconductive device 320 and of the connecting points 318 a and 318 b onthe top surface 312 of the conducting ring 310, and the number of theconductive device 320 and of the connecting points 318 a and 318 baccording to the design requirements.

After the redistribution layer 130 is patterned, the passive componentportion 134 of FIG. 9 would have a similar thickness, thereby ensuringthe function of itself as an integrated passive device (IPD).

It is to be noted that the connection relationships and materials of theelements described above will not be repeated in the followingdescription, and only aspects related to other types of semiconductorelectroplating system and operating method will be described.

FIG. 19 is a top view of a semiconductor electroplating system 300 aaccording to an embodiment of the present invention. The semiconductorelectroplating system 300 a includes the conducting ring 310 andconductive devices 320 a and 320 b. The difference between thisembodiment and the embodiment shown in FIG. 16 is that herein thesemiconductor electroplating system 300 a has two conductive devices 320a, 320 b and five connecting points 318 c, 318 d, 318 e, 318 f, 318 g.The connecting point 318 c is connected to the conducting wire 302 whichprovides the current. Two ends 322 a and 324 a of the conductive device320 a are respectively connected to the two connecting points 318 d, 318e of the conducting ring 310, and two ends 322 b, 324 b of theconductive device 320 b are respectively connected to the two connectingpoints 318 f and 318 g of the conducting ring 310.

In this embodiment, when the wafer 110 a in FIG. 8 located in theconducting ring 310 is immersed in the plating solution, the conductivedevice 320 a can lead a partial current that passes through theconnecting point 318 d of the conducting ring 310 to the connectingpoint 318 e, and the conductive device 320 b can lead a partial currentthat passes through the connecting point 318 f of the conducting ring310 to the connecting point 318 g, thereby reducing the thickness of theredistribution layer 130 formed adjacent to the connecting points 318 dand 318 f and increasing the thickness of the redistribution layer 130formed adjacent to the connecting point 318 e and 318 g. As a result,the thickness uniformity of the redistribution layer 130 that is to bepatterned is improved.

FIG. 20 is a flow chart of an operating method of a semiconductorelectroplating system according to an embodiment of the presentinvention After the isolation layer 120 of FIG. 8 is formed, in step S1b, two connecting points of two ends of at least one conductive pieceare movably connected to a ring-shaped track of a conducting ring. Theconductive piece overlaps a portion of the conducting ring. Next, instep S2 b, the wafer having the isolation layer is disposed in theconducting ring. In step S3 b, the conducting ring is immersed in aplating solution. Finally, in step S4 b, the conducting ring isenergized to form the redistribution layer that is to be patterned onthe isolation layer. A partial current passing through one of theconnecting points transmits to the other connecting point through theconductive piece. The details of the aforementioned steps will bedisclosed in the following descriptions.

FIG. 21 is a top view of a semiconductor electroplating system 300 baccording to an embodiment of the present invention. The semiconductorelectroplating system 300 b includes a conducting ring 310 a and atleast one conductive piece 330. The conducting ring 310 a can be used tocarry semiconductor structure of FIG. 8. The conducting ring 310 a has aring-shaped track 313. Each of the two ends 332 and 334 of theconductive piece 330 has a connecting point that is movably connected tothe ring-shaped track 313 of the conducting ring 310 a. For instance,the connecting points of the two ends 332 and 334 of the conductivepiece 330 may be protrusions, and the ring-shaped track 313 may be aslot that can be coupled to the protrusions, or, the connecting pointsof the two ends 332 and 334 of the conductive piece 330 may be metalwheels, and the ring-shaped track 313 may be a slot that can be coupledto the wheels. After the conductive piece 330 is connected to thering-shaped track 313 of the conducting ring 310 a, the conductive piece330 overlaps a portion of the conducting ring 310 a, and the conductivepiece 330 can be stressed to move on and along the ring-shaped track 313in a clockwise direction D3 or a counterclockwise direction D4. Afterthe semiconductor electroplating system 300 b of FIG. 21 is assembled,the wafer 110 a having the isolation layer 120 shown in FIG. 8 can bedisposed in the conducting ring 310 a.

In this embodiment, the conducting ring 310 a has the top surface 312,the sidewall 314, and the supporting surface 316 which are sequentiallyconnected. The conductive piece 330 and the ring-shaped track 313 areboth disposed on the top surface 312 of the conducting ring 310 a. Thesidewall 314 surrounds the accommodating space 311, and the supportingsurface 316 is protruding from the accommodating space 311, such thatthe top surface 312, the sidewall 314, and the supporting surface 316form a ladder structure. The accommodating space 311 can hold the wafer110 a of FIG. 8, and the wafer 110 a can be disposed on the supportingsurface 316, such that the wafer 110 a is surrounded by the sidewall314. The first surface 111 of the wafer 110 a (front surface) faces thesupporting surface 316.

After the wafer 110 a of FIG. 8 is disposed in the conducting ring 310a, the conducting ring 310 a and the wafer 110 a that has the isolationlayer 120 may be immersed in a plating solution and energized, thecircuit can flow into the conducting ring 310 a through the conductingwire 302.

As shown in FIG. 21 and FIG. 18. After the conducting ring 310 a isenergized, the redistribution layer 130 that is to be patterned can beformed on the isolation layer 120. The conductive piece 330 can transmita partial current that passes through the connecting point of the end332 to the connecting point of the other end 334, such that theredistribution layer 130 on the second surface 113 (back surface) has auniform thickness. In this embodiment, the conductive piece 330 locatedon the conducting ring 310 a has the function of dispersing the current.When the wafer 110 a of FIG. 8 located in the conducting ring 310 a isimmersed in the plating solution, the conductive piece 330 can lead apartial current that passes through the connecting point of one end 332in contact with the conducting ring 310 a to a specific place (such asthe connecting point of the other end 334), thereby reducing thethickness of the redistribution layer 130 formed adjacent to the end 332of the conductive piece 330 and increasing the thickness of theredistribution layer 130 formed adjacent to the end 334 of theconductive piece 330. As a result, the thickness uniformity of theredistribution layer 130 that is to be patterned can be improved.

The designer may slide the conductive piece 330 on the ring-shaped track313 of the top surface 312 of the conducting ring 310 a according to thedesign requirements, such that the positions of the two ends 332 and 334of the conductive piece 330 on the top surface 312 are adjusted.

Although the present invention has been described in considerable detailwith reference to certain embodiments thereof, other embodiments arepossible. Therefore, the spirit and scope of the appended claims shouldnot be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims.

What is claimed is:
 1. A semiconductor electroplating system,comprising: a conducting ring for carrying a wafer, and having at leasttwo connecting points, wherein the wafer has a first surface and anopposite second surface, and an isolation layer is located on the secondsurface; and at least one conductive device having two ends that arerespectively connected to the connecting points of the conducting ring,wherein when the conducting ring is immersed in a plating solution andis energized, a redistribution layer that is to be patterned is formedon the isolation layer, wherein the conductive device is used fortransmitting a partial current passing through one of the connectingpoints to the other connecting point.
 2. The semiconductorelectroplating system of claim 1, wherein the conducting ring has a topsurface, a sidewall, and a supporting surface which are sequentiallyconnected, and the sidewall surrounds an accommodating space, and thesupporting surface protrudes from the accommodating space, such that thetop surface, the sidewall and the supporting surface form a ladderstructure.
 3. The semiconductor electroplating system of claim 2,wherein the wafer is located on the supporting surface, and issurrounded by the sidewall.
 4. The semiconductor electroplating systemof claim 2, wherein the first surface of the wafer faces the supportingsurface.
 5. The semiconductor electroplating system of claim 2, whereinthe connecting points and the conductive device are located on the topsurface of the conducting ring.
 6. The semiconductor electroplatingsystem of claim 1, wherein the conductive device is an electric wire. 7.A semiconductor electroplating system, comprising: a conducting ring forcarrying a wafer, and having a ring-shaped track, wherein the wafer hasa first surface and an opposite second surface, and an isolation layeris located on the second surface; and at least one conductive piecehaving two ends, wherein each of the ends has a connecting point whichis movably connected to the ring-shaped track of the conducting ring,and the conductive piece overlaps a portion of the conducting ring; whenthe conducting ring is immersed in a plating solution and is energized,a redistribution layer that is to be patterned is formed on theisolation layer, wherein the conductive piece is used for transmitting apartial current passing through one of the connecting points to theother connecting point.
 8. The semiconductor electroplating system ofclaim 7, wherein the conducting ring has a top surface, a sidewall, anda supporting surface which are sequentially connected, and the sidewallsurrounds an accommodating space, and the supporting surface protrudesfrom the accommodating space, such that the top surface, the sidewalland the supporting surface form a ladder structure.
 9. The semiconductorelectroplating system of claim 8, wherein the wafer is located on thesupporting surface, and is surrounded by the sidewall.
 10. Thesemiconductor electroplating system of claim 8, wherein the firstsurface of the wafer faces the supporting surface.
 11. The semiconductorelectroplating system of claim 8, wherein the ring-shaped track islocated on the top surface of the conducting ring, and the two ends ofthe conductive piece are movably disposed on the ring-shaped track.